Welcome to the new site for BeagleBoard.org GSoC 2024 projects!



How to participate?

Contributors are expected to go through the list of ideas dropdown below and join the discussion by clicking on the Discuss on forum button. All ideas have colorful badges for Complexity and Size for making the selection process easier for contributors. Anyone is welcome to introduce new ideas via the forum gsoc-ideas tag. Only ideas with sufficiently experienced mentor backing as deemed by the administrators will be added here.



High complexity

350 hours

Medium complexity

175 hours

Low complexity

90 hours

FPGA gateware improvements Medium complexity 175 hours

Low-latency I/O RISC-V CPU core in FPGA fabric

BeagleV-Fire features RISC-V 64-bit CPU cores and FPGA fabric. In that FPGA fabric, we’d like to implement a RISC-V 32-bit CPU core with operations optimized for low-latency GPIO. This is similar to the programmable real-time unit (PRU) RISC cores popularized on BeagleBone Black.

Goal: RISC-V-based CPU on BeagleV-Fire FPGA fabric with GPIO
Hardware Skills: Verilog, verification, FPGA
Software Skills: RISC-V ISA, assembly, Linux
Possible Mentors: Cyril Jean, Jason Kridner

Linux kernel improvements Medium complexity 350 hours

Update beagle-tester for mainline testing

Utilize the beagle-tester application and Buildroot along with device-tree and udev symlink concepts within the OpenBeagle continuous integration server context to create a regression test suite for the Linux kernel and device-tree overlays on various Beagle computers.

Goal: Execution on Beagle test farm with over 30 mikroBUS boards testing all mikroBUS enabled cape interfaces (PWM, ADC, UART, I2C, SPI, GPIO and interrupt) performing weekly mainline Linux regression verification

Linux kernel improvements Medium complexity 175 hours

Upstream wpanusb and bcfserial

These are the drivers that are used to enable Linux to use a BeagleConnect Freedom as a SubGHz IEEE802.15.4 radio (gateway). They need to be part of upstream Linux to simplify on-going support. There are several gaps that are known before they are acceptable upstream.

Goal: Add functional gaps, submit upstream patches for these drivers and respond to feedback
Hardware Skills: wireless communications
Software Skills: C, Linux
Possible Mentors: Ayush Singh, Jason Kridner

Automation and industrial I/O Medium complexity 175 hours

librobotcontrol support for newer boards

Preliminary librobotcontrol support for BeagleBone AI, BeagleBone AI-64 and BeagleV-Fire has been drafted, but it needs to be cleaned up. We can also work on support for Raspberry Pi if UCSD releases their Hat for it.

Goal: Update librobotcontrol for Robotics Cape on BeagleBone AI, BeagleBone AI-64 and BeagleV-Fire
Hardware Skills: basic wiring, motors
Software Skills: C, Linux
Possible Mentors: Deepak Khatri, Jason Kridner

RTOS/microkernel imporvements Medium complexity 350 hours

Upstream Zephyr Support on BBAI-64 R5

Incorporating Zephyr RTOS support onto the Cortex-R5 cores of the TDA4VM SoC along with Linux operation on the A72 core. The objective is to harness the combined capabilities of both systems to support BeagleBone AI-64.

Goal: submit upstream patches to support BeagleBone AI-64 and respond to feedback
Hardware Skills: Familiarity with ARM Cortex R5
Software Skills: C, RTOS
Possible Mentors: Dhruva Gole, Nishanth Menon

Deep Learning Medium complexity 350 hours

Enhanced Media Experience with AI-Powered Commercial Detection and Replacement

Leveraging the capabilities of BeagleBoard’s powerful processing units, the project will focus on creating a real-time, efficient solution that enhances media consumption experiences by seamlessly integrating custom audio streams during commercial breaks.

Goal: Build a deep learning model, training data set, training scripts, and a runtime for detection and modification of the video stream.
Hardware Skills: Ability to capture and display video streams using BeagleBone AI-64
Possible Mentors: Jason Kridner, Deepak Khatri

Creative AI Medium complexity 350 hours

Embedded differentiable logic gate networks for real-time interactive and creative applications

This project seeks to explore the potential of creative embedded AI, specifically using Differentiable Logic (DiffLogic), by creating a system that can perform tasks like machine listening, sensor processing, sound and gesture classification, and generative AI.

Goal: Develop an embedded machine learning system on BeagleBone that leverages Differentiable Logic (DiffLogic) for real-time interactive music creation and environment sensing.
Hardware Skills: Audio and sensor IO with Bela.io
Software Skills: Machine learning, deep learning, BeagleBone Programmable Real Time Unit (PRU) programming (see PRU Cookbook).
Possible Mentors: Jack Armitage, Chris Kiefer

Visit our forum to see newer ideas being discussed!


You can also check our our Old GSoC Ideas and Past Projects for inspiration.